The launch of Raspberry Pi 5 represented a significant change from previous models. Building chips that run faster and use less power, while continuing to support 3.3 V I/O, presents real, exciting challenges. Our solution was to split the main SoC (system on chip) in two – the compute half, and the I/O half – and put a fast interconnect (4-lane PCIe Gen 3) between them. The SoC on Raspberry Pi 5 is the Broadcom BCM2712, and the I/O processor (which used to be known in the PC world as the ‘southbridge’) is Raspberry Pi RP1.
Along with all the usual peripherals – USB, I2C, SPI, DMA, and UARTs – RP1 included something a bit more interesting. One of RP2040's distinguishing features was a pair of PIO blocks, deceptively simple…
